English
Last-modified: 2011-04-05 (火) 14:24:55 (806d)
Profile †
Yusuke Funaya
- Doctor Course Student
- Ultra-Highspeed Information Processing Algorithms, Kobayashi Lab.
- Graduate School of Information Sciences, Tohoku University, Japan
- Research Fellow of the Japan Society for the Promotion of Science (2009.04~2011.03)
Research Topics †
- Vector supercomputers.
- Three-dimensional integrated circuits.
- Memory architectures.
Publications †
2011 †
- 実アプリケーションによるチップマルチベクトルプロセッサの消費エネルギ評価
- 永岡龍一, 佐藤義永, 船矢祐介, 撫佐昭裕, 江川隆輔, 滝沢寛之, 小林広明.
- 第9回情報シナジー研究会, Sendai, Japan, February 2011. (in Japanese)
2010 †
- Design and Early Evaluation of a 3-D Die Stacked Chip Multi-Vector Processor
[DOI][pdf]
- Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa and Hiroaki Kobayashi.
- IEEE International 3D System Integration Conference (3DIC) 2010, Munich, Germany, November 2010.
- Cache Partitioning Strategies for 3-D Stacked Vector Processors
[DOI][pdf]
- Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi.
- IEEE International 3D System Integration Conference (3DIC) 2010, Munich, Germany, November 2010. (Poster)
2009 †
- 3次元積層技術による次世代ベクトルキャッシュの設計と評価
[pdf]
- 船矢祐介, 永岡龍一, 江川隆輔, 滝沢寛之, 小林広明.
- 次世代スーパーコンピューティングシンポジウム2009, Tokyo, Japan, pp.67-68, Octorber 2009. (Poster, in Japanese)
- 3D On-Chip Memory for the Vector Architecture
[DOI][pdf]
- Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi.
- IEEE International Conference on 3D System Integration (3D IC) 2009, San Francisco, USA, September 2009. (Poster)
- メモリ積層型3次元ベクトルプロセッサの評価
[pdf]
- 船矢祐介, 江川隆輔, 滝沢寛之, 小林広明.
- 先進的計算基盤システムシンポジウム SACSIS 2009, Hiroshima, Japan, pp.171-172, May 2009. (Poster, in Japanese)
- Early Evaluation of a Memory-Stacked Vector Processor
[pdf]
- Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi.
- COOL Chips XII: IEEE Symposium on Low-Power and High-Speed Chips, Yokohama, Japan, pp.165, April 2009. (Poster)
2008 †
- Thread Scheduling for Multi-Core Processors
[web]
- Master Thesis, Tohoku University, 2008. (in Japanese)
2007 †
- Analysis of hardware resource conflicts for runtime performance prediction of SMT processors
[pdf]
- Masayuki Sato, Yusuke Funaya, Isao Kotera, Hiroyuki Takizawa and Hiroaki Kobayashi.
- Information Technology Letters, Vol.6, No.6, pp.67-70, 2007. (in Japanese)
2006 †
- Thread Scheduling Based on the Thread Characteristics for Multi-Core Processors
[pdf]
- Yusuke Funaya, Isao Kotera, Hiroyuki Takizawa and Hiroaki Kobayashi.
- Information Technology Letters, Vol.5, No.5, pp.37-40, 2006. (in Japanese)
- マルチコアプロセッサのスケジューリングに関する研究
[pdf]
- Graduation Thesis, Tohoku University, 2006. (in Japanese)
