Last update: April 26, 2012.

Masayuki Sato (Postdoctoral)

Research Division on Supercomputing Systems,
Cyberscience Center, Tohoku University.
Email: masayuki at sc dot isc dot tohoku dot ac dot jp
Masayuki Sato's bibliography

Research Interests

  • Computer Architecture (Parallel Architecture, Cache Memory)
  • Energy-Aware Computing

Publications

Reviewed Journals

  • 佐藤雅之，船矢祐介，小寺功，滝沢寛之，小林広明， ”SMTプロセッサの実行時性能予測のためのハードウェアリソース競合解析，” 第6回情報科学技術フォーラム(FIT2007)情報科学技術レターズ，pp67-70，Vol.6，2007．

Reviewed Papers

  • Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "A Voting-Based Working Set Assessment Scheme for Dynamic Cache Resizing Mechanisms," In Proceedings of IEEE International Conference on Computer Design (ICCD 2010), pp.98-105, 2010. [LINK]
  • Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "A Majority-based Control Scheme for Way-Adaptable Caches," In Lecture Notes in Computer Science, Volume 6310/2011, pp 16-28, 2010, Springer. [LINK]
  • Masayuki Sato, Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "A Cache-Aware Thread Scheduling Policy for Multi-Core Processors," In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2009), pp.109-114, 2009, ACTA Press. [LINK]

Reviewed Posters

  • 東方雄亮, 佐藤雅之, 江川隆輔, 滝沢寛之, 小林広明, "ウェイ適応型キャッシュの高エネルギ効率化のためのデッドブロック早期追い出しポリシ," 先進的計算基盤シンポジウムSACSIS2012, pp.4--5, 2012.
  • Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "A Capacity-Efficient Insertion Policy for Dynamic Cache Resizing Mechanisms," In Proceedings of ACM International Conference on Computing Frontiers, pp.265-267, 2012.
  • Takumi Takai, Yusuke Tobo, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "A Bypass Mechanism for Way-Adaptable Caches," In Poster Proceedings of COOLChips XV, Poster No. 11, 2012. (Best Poster Award)
  • 東方雄亮, 佐藤雅之, 江川隆輔, 滝沢寛之, 小林広明, "ウェイ適応型キャッシュのための低消費エネルギ指向挿入ポリシ," 先進的計算基盤シンポジウムSACSIS2011, pp.213-214, 2011.
  • Yusuke Tobo, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi, "A Power-Aware Insertion Policy for the Way-Adaptable Cache Mechanism", In Poster Proceedings of COOLChips XIV, Poster No. 20, 2011.
  • Masayuki Sato, Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi, "Working Sets based Thread Scheduling with Cache Partitioning," In Poster Abstracts of The Eighteenth International Conference on Parallel Architecture and Compilation Techniques (PACT'09), pp.12, 2009. [LINK]

Non-Reviewed Papers

  • 佐藤雅之，小寺功，江川隆輔，滝沢寛之，小林広明， ”ワーキングセット評価に基づくスレッドスケジューリング，” 並列/分散/協調処理に関する「仙台」サマーワークショップ， 2009．

Academic Dissertations

  • Masayuki Sato, "A Hardware-Software Co-designed Cache Memory System for Energy-efficient Microprocessors," doctor thesis, Graduate School of Information Sciences, Tohoku University, 2012 (平成23年度).
  • 佐藤雅之，”ワーキングセット評価に基づくスレッドスケジューリングに関する研究，” 東北大学，大学院情報科学研究科，修士論文，平成20年度．
  • 佐藤雅之，”マルチスレッドプログラムの実行時性能予測に関する研究，” 東北大学，工学部，機械知能航空工学科，学士論文，平成18年度．